1. Field of the Invention
The present invention relates to a digital noise generator for generating pseudo-random noise subjected to amplitude control and pulse code modulation (hereinafter referred to as PCM) coding. The digital noise generator is used to alleviate the listener's discomfort occurring during so-called inactivity periods when no signal is transmitted from the speaker side. Specifically, the digital noise generator is employed in, for instance, digital speech interpolation (hereinafter referred to as the DSI) equipment in which only signals with voice activity are transmitted among digitized telephone speech signals, digital circuit multiplication equipment (hereinafter referred to as the DCME) which is a combination of the DSI equipment and a low-bit-rate speech coding technique, and a voice packet transmission equipment.
2. Description of the Related Arts
Conventionally, various circuit configurations are known as digital noise generators for generating pseudo-random noise.
FIG. 2 illustrates an example of a configuration of a conventional digital noise generator. This configuration is disclosed in Japanese Utility Model Publication No. 12446/1989.
This digital noise generator has a pseudo-random bit sequence generator 3 which is composed of an exclusive-OR circuit 1 and an n-bit shift register 2.
Furthermore, this digital noise generator has a pulse amplitude modulation circuit (hereinafter referred to as the PAM circuit) 4. The PAM circuit 4 includes both a weighting circuit 5 including a plurality of weighting resistors 6 and an adder 7 for adding outputs of the weighting circuit 5 together.
A description will now be given of the operation of this digital noise generator.
The exclusive-OR circuit 1 fetches an output and intermediate output of the shift register 2, performs an exclusive-OR operation with respect to these outputs, and feeds back the computed result to the shift register 2. Here, by the intermediate output of the shift register 2 is meant a signal representing the value of a predetermined bit of the n-bit shift register 2.
As a result of the above-described configuration, the value of the bits of the shift register 2 becomes one which is generally called a pseudo-random bit sequence.
Furthermore, since each bit of the shift register 2 is connected to one end of each weighting resistor 6, a signal obtained by adding the outputs of the weighting circuit 5 by means of the adder 7 becomes a signal representing a value in which the values of the bits of the shift register 2 are weighted and added together, i.e., a pulse amplitude-modulated signal.
The signal thus obtained is called the pseudo-random noise signal. This pseudo-random noise signal is used as white noise in the aforementioned DSI equipment and other similar equipments. In such an application, it is necessary to set the number n of the bits of the shift register 2 to a sufficiently large magnitude.
FIG. 3 illustrates a second example of the circuit configuration of the digital noise generator in accordance with the prior art.
In this circuit configuration, an improvement is made on the configuration of the weighting circuit 5 in the circuit configuration shown in FIG. 2. This circuit includes a sequence generator 13 like the generator 3 of FIG. 2. This sequence generator 13 specifically comprises an exclusive-OR circuit 11 that receives as inputs an output and an intermediate output of an n-bit shift register 12. The exclusive-OR 11 also reinputs its output to the shift register 12. Each bit of the shift register 12 is connected as a data bit to a PAM circuit 14. This PAM circuit includes a weighing circuit 15 and an adder 17.
In other words, a weighting circuit 15 in FIG. 3 includes an n-number of AND circuits 18 (1-n) and an n-number of scale factor circuits 19 (1-n) that are both connected to output terminals of the AND circuits 18.
The bit data of the shift register 12 are respectively inputted to the input terminals of the AND circuits 18, and an amplitude control signal is also inputted thereto from an external circuit.
The amplitude control signal is used to select which bit of the shift register 12 is to be added by an adder 17.
That is, each of the AND circuits 18 outputs the bit data of the shift register 12 to a corresponding one of the scale factor circuits 19 (1-n) in response to the amplitude control signal. Each of the scale factor circuits 19 weights the data supplied from the corresponding AND circuit 18, and outputs the result to the adder 17. The pseudo-random noise signal is outputted from the adder 17 in the same way as the prior art shown in FIG. 2.
Accordingly, in this prior art it is possible to control the amplitude of the pseudo-random noise signal by adjusting the number of bits to be added by means of the amplitude control signal.
FIG. 4 illustrates a third example of the circuit configuration of the conventional digital noise generator. A sequence generator 23 similar to those of FIGS. 2 and 3 is shown that includes an exclusive-OR circuit 21 having inputs from an intermediate output and an output of an n-bit shift register 22. The exclusive-OR 21 also reinputs its output to the shift register 22. Each bit output from the shift register 22 is input as a data bit to a PAM circuit 24, similar to that shown in FIG. 3, that includes a weighing circuit 25 and an adder 27. The weighing circuit comprises a group of AND circuits 28 (1-n) each connected to a corresponding scale factor circuit 29 (1-n). The bit data of the shift register 22 are respectively input to the input terminals of the AND circuits 28 (1-n)along with an input from an amplitude control signal similar to that shown in FIG. 3. Outputs of each of the AND circuits 28 (1-n) are then input to a corresponding scale factor circuit 29 (1-n), also similar to those shown in FIG. 3. Each bit output from the weighing circuit 25 is then input to an adder 27 in the same manner as in the FIG. 3 embodiment.
The configuration of this digital noise generator is such that a PAM/PCM converter 30 is added to the configuration shown in FIG. 3.
In other words, the pseudo-random noise signal outputted from an adder 27 is a pulse amplitude-modulated signal, i.e., a PAM signal. In cases where a PCM noise signal is required in DSI equipment or the like, it is necessary to generate a PCM pseudo-random noise signal by converting the PAM signal to a PCM signal. The PAM/PCM converter 30 performs this PAM/PCM conversion.
The digital noise generators provided with the above-described configurations have the following problems:
1) A large-scale circuit configuration is necessary for securing the randomness of the pseudo-random noise signal.
In other words, the greater the number of bits of a shift register subject to addition by the adder, the greater the randomness of the pseudo-random noise signal.
Accordingly, in order to enhance the randomness of the pseudo-random noise signal, it is significant to increase the number of bits of the shift register. However, an increase in the number of bits of the shift register leads to greater numbers of AND circuits and scale factor circuits both corresponding to the respective bits. These are a factor enlarging the circuit configuration.
Meanwhile, if the weighting by the use of the scale factor circuits is effected with a greater weight, it is possible to enhance the randomness of the pseudo-random noise signal without resulting in an increased number of bits of the shift register. In this case, however, the code length becomes longer in correspondence with the degree of weighting, so that the configuration of the adder becomes complicated.
2) In order to generate the pseudo-random noise signal of PCM, a PAM/PCM converter is necessary, so that the circuit configuration becomes complicated.